用于FPGA的USB2.0虚构逻辑分析仪的设计与实现

The logistic analyzer bulk of foreword 　 tradition giant, price number of costly, passageway is limited, and be collected in data, transmit, memory, show wait for a respect to be put in a lot of limitation, affected its greatly applying mediumly actually. The FPGA chip that chooses tall function undertakes data processing, make full use of the powerful processing function of PC, cooperate LabView graph to change the fictitious and logistic analyzer of language research and development, its data processing rises greatly with transmission rate, applicability is great increase, its show, operation interface and low cost have huge advantage and development perspective than traditional logistic analyzer. The EP1C3 of parts of an apparatus of Cyclone series FPGA that this design of working principle 　 chooses Altera company undertakes counting occupying collect and be handlinged, SRAM is received outside, use at the memory of data. The PIC that the system passes tall function is odd PIC18F6620 completes an engine the communication with PC, receive what PC gives out to spark, the data after configure information and controlling a system to will collect processing uploads to show to PC. Odd the interface of machine and a PC uses the implementation of interface chip CP2102 that accords with USB2.0 standard. Above all, PC is sent to FPGA spark word information, data collects control information and open data to collect signal; Odd a machine DAC is received to produce the door to be restricted outside sending data to come voltage; The input signal that collects is restricted with this through high speed comparator voltage undertakes comparative, it is in order to decide its are worth 0 or 1. After receiving the open data that issues to PC to collect signal, FPGA collects data by the working way of set, shift of each passageway data inputs FPGA interior cache and stock exterior SRAM. FPGA collects what store in cache data and set spark word, spark means and screen undertake comparative. Once accord with,strike hair requirement, install spark mark, the record sparks the position. After data collects the check the number to set, FPGA is sent to PC collect the signal that finish. Go up a machine after receiving this signal, send read access to occupy a command, the system reads stoping market data and show on PC screen. Systematic functional-block diagram is shown 1 times like the graph. Graph system of 　 of of 1 system functional-block diagram sparks module design 　 sparks the core part that module is whole system, basically include sampling clock to choose module, spark n is installed and hit hair circuit 3 parts. Sampling clock chooses module 　 clock to choose module to be used at choosing sampling frequency. The clock source that can offer an alternative includes: Exterior clock (by active brilliant brace up offer) , odd the PWM clock of a generation of machine PWM module, exterior clock is inputted (offer by additional facility) , with signal of word of N a movement in martial arts the input regards sampling as clock. Touch hair n to install 　 to touch hair n to use definite system to identify the n of on any account of sampling signal correctly. This module is mixed by TLC5615 of serial digital-to-analogue converter LT1721 of high speed comparator is formed. Before sampling begins, odd a machine send to DAC touch hair n data, the n signal after changeover (limits sends high speed comparator from 0~+5V) . Touching hair circuit 　 to touch the effect that sends circuit is to decide sampling signal is contented strike hair requirement, arise respectively strike hair action. When the signal that should collect satisfies what the user installs to strike hair requirement, systematic record sparks the position arises spark on signal announcement machine read take, indication sampling data. Of this second design touch hair circuit to have 3 kinds to spark optionally mode: Spark instantly, spark orderly and run paralell spark. Spark instantly 　 is become a machine give out to FPGA spark instantly spark word and after beginning sampling to dictate, FPGA begins sampling and arise instantly spark signal. Sampling circuit stocks the signal that collects external in SRAM, till be collected,sampling stops after formulary check the number, up machine give out sampling to end signal, inform its are read take sampling data. Read below this means those who answer spark spot position is 0. Spark orderly 　 this means installed a 8 alignment to spark, press when the signal of the passageway that be measured only ordinal and contented spark when 8 alignment of word place set, ability generation sparks signal. In the meantime, for the flexibility of the operation, still added screen. Be like pair of some data is not sensitive, can its corresponding screen the setting is 0, in decide when striking hair requirement incorrect this undertake detecting. The operation sparks orderly means, can to random a passageway chooses most the alignment of 8 length undertakes sparking. When undertaking sparking installing, spark except the setting means (the choice sparks orderly) and undertake sampling frequency chooses beyond, still need to undertake the passageway chooses, spark word and screen setting. Algorithmic source program of its Verilog HDL is as follows: 12 3 of on one page issues one page

　　引言

　　传统的逻辑分析仪体积简单、价钱低廉、通道数目有限，而且在数据采集、传输、存储、显示等方面存在诸多限度，在很大程度上影响了其在理论中的应用。选用高性能的FPGA芯片进行数据措置，充分操纵PC的强大措置性能，配合LabView图形化说话研发的虚构逻辑分析仪，其数据措置和传输速度大大进步，合用性极大增强，其显示、操作界面和低廉的本钱较之传统的逻辑分析仪存在极大的劣势和成长前景。

　　工作事理

　　本设计选用Altera公司的Cyclone系列FPGA器件EP1C3进行数据采集和措置，外接SRAM，用于数据的存储。系统经由过程高性能的PIC单片机PIC18F6620实现与PC的通信，领受PC发出的触发、设置装备摆设信息并节制系统将采集措置后的数据上传至PC显示。单片机与PC的接口操纵合适USB2.0规范的接口芯片CP2102实现。

　　首先，PC向FPGA发送触发字信息、数据采集节制信息和开启数据采集信号；单片机发送数据至外接DAC发生门限电压；采集到的输入信号经由过程高速比较器与此门限电压进行比较，以确定其值为0或1。领受到PC发出的开启数据采集信号后，FPGA按设定的工作体例采集数据，各通道数据移位输入FPGA内部缓存并存入外部SRAM。FPGA将缓存中存储的采集数据与设定的触发字、触发体例和屏障位进行比较。一旦合适触发前提，则设置触发标记，记实触发地位。当数据采集至设定的点数后，FPGA向PC发送采集实现信号。上位机领受到此信号后，发送读取数据呐喊，系统读回采集数据并在PC屏上显示。系统性能框图如图1所示。

　　图1 系统性能框图

　　系统触发模块设计

　　触发模块是整个系统的核心部门，首要包括采样时钟选择模块、触发电平设置和触发电路三个部门。

　　采样时钟选择模块

　　时钟选择模块用于选择采样频率。可供选择的时钟源包括：外部时钟(由有源晶振供给)、单片机PWM模块发生的PWM时钟、外部时钟输入(由额外的行动措施供给)、以第N路数字信号输入作为采样时钟。

　　触发电平设置

　　触发电平用来确定系统正确识别采样信号的凹凸电平。该模块由串行数模转换器TLC5615和高速比较器LT1721组成。采样起头前，单片机向DAC发送触发电平数据，转换后的电平信号(规模从0~+5V)送入高速比较器。

　　触发电路

　　触发电路的感化是判定采样信号是否满足触发前提，并分袂发生触策动作。当采集的信号满足用户设置的触发前提时，系统记实触发地位并发生触发信号通知上位机读取、显示采样数据。本次设计的触发电路存在三种可选的触发模式：立即触发、挨次触发和并行触发。

　　立即触发

　　当上位机向FPGA发出立即触发触发字和起头采样指令后，FPGA起头采样并立即发生触发信号。采样电路将采集到的信号存入外部的SRAM中，直至采集到划定的点数后遏制采样，向上位机发出采样竣事信号，通知其读取采样数据。此体例下读回的触发点地位为0。

　　挨次触发

　　该体例设置了一个8位的序列触发，只有当被测通道的信号按依次满足触发字所设定的8位序列时，才发生触发信号。同时，为了操作的灵敏性，还插手了屏障位。若对某一位的数据不敏感，能够将其对应的屏障位设置为0，在判定触发前提时不合错误该位进行检测。

　　操作挨次触发体例，能够对任意一个通道选择最多8位长度的序列进行触发。在进行触发设置时，除设置触发体例(选择挨次触发)和进行采样频率选择以外，还需要进行通道选择、触发字和屏障位设置。其Verilog HDL算法源挨次如下：
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发布日期：2009-1-1　【返回】