低频数字相位(频率)测量的CPLD实现

Science and technology is measured in the electron in, measuring frequency is one of the basiccest measurement. Phasic measuring instrument is the commonly used instrument of electronic area, measuring frequency currently basically is to apply wait for precision to measure Suo Xianghuan of frequency, PLL to measure the method of the photograph. Consider to discover, wait for precision to measure frequency law to have the characteristic that maintains constant high accuracy inside the whole range that measure frequency, but this principle cannot be used at measuring phasic. It is OK that PLL Suo Xianghuan is measured the precision such as implementation is measured, but circuit is debugged more complex. Accordingly, the test method that chooses to measure look doctrine to measure photograph appearance as low frequency directly [1, 2, 3, 4] . The low frequency of the design measures photograph appearance, satisfy index of the following science and technology: A. Frequency 20-20KHz; B. Input Ω of impedance ≥ 100K; C. Phasic measure absolutely error ≤ 1 degree; D. Have frequency to measure display a function with the number; E. Show phasic reading is 0 degrees- - 359 degrees. 　 of principle of 1 system work pursues 1 measure frequency to if the graph is shown 1 times,measure principle of work of system of 　 of block diagram of phase system principle, when the system moves, above all by sheet piece machine send to clear signal through Clr control line, the computation module of the CPLD that start, below the action of module of CPLD built-in control of the design, the discrepancy that records AB two-phase the mark frequency inside time interval several (measure photograph tally) , also record next A photographs at the same time the mark frequency inside a cycle several (the tally that measure frequency) , after this is measured frequency and measure photograph tally to be in hold position, send Right signal to make clear at the same time finish measure frequency to measure the count of the photograph, odd a machine is OK read data. Odd the data of machine and a CPLD uses independent interface means, such designs are more agile, need not suffer sheet piece the influence of sequential of machine bus line. By ADD[0. .2] undertakes controlling, read respectively take the 19 digit in measuring frequency to measure photograph tally to occupy, coexist at sheet piece in machine, have follow-up consideration. Odd after the operation of a machine data that finish, income data translate into 10 into make, send show board undertake indication. Show board share 8 numbers to be in charge of, among them, before 5 are used at showing frequency (most greatly 20000Hz) , hind 3 show phasic (most greatly 359 degrees) . In CPLD design, according to computation, choose measure frequency, measure photograph tally length to all be 19, when mark frequency signal is 10MHz, phasic measure precision to be less than 1 degree. If use 89C51 only, its have 16 only from the tally of the belt, and come true not easily at the same time measure frequency to measure the function of the photograph. Reason chooses CPLD to come true its measure frequency to measure the computation function of the photograph, designed independent data interface, so that with sheet piece machine trade data [5, 6] . 2 CPLD measures frequency to measure 2 CPLD of graph of 　 of principle of photograph module job to measure frequency to if the graph is shown 2 times,measure 　 of block diagram of in-house principle, used VHDL language to design finish the digital chip that measures frequency to measure photograph computation function. Whole chip by the tally that measure frequency, measure selector of part of photograph tally, control, data and test to use scale down implement 5 parts composition. Controlling a share basically is to use condition machine principle, designed detect the control circuit of a cycle that measure frequency. It is in Clr signal tall when, start measure frequency to measure photograph tally, right now, condition machine is in computation job status; When A photograph the first ascendant edge comes when, measure frequency to measure photograph tally to be started at the same time, begin computation; When B photograph the first ascendant edge comes when, control part control measures photograph tally to stop computation; When A photograph the 2nd ascendant edge comes when, control controls the tally that measure frequency to stop computation partly, send a computation to finish signal Right at the same time; After this measures frequency to measure photograph tally to be in hold position. Odd piece when machine reading, through installing Add[0. The address of.2] data selector chooses an end, ordinal 19 data in sending the tally that measure frequency, 8 a group, from Xcout[0. .7] port sends, odd the 19 digit in needing cent 3 times to read the tally that measure frequency seize an opportunity, data chooses the setting that tell end for 001, 010, 011; Manage together, odd a machine also need cent 3 times to read the 19 digit in measuring photograph tally to occupy, data chooses the setting that tell end for 100, 101, 110. Go to the lavatory for the test, designed a test to use scale down implement, this scale down implement coefficient can alter in VHDL source program, if be 1000, the 10M of mark frequency signal that will use when the test undertakes 1000 scale down, the frequency after scale down is 10KHz, as it happens is in 20-20KHz limits inside. 3 sheet piece engine order 　 is shown 3 times like the graph, after systematic electrify, above all by sheet piece machine send a to clear signal, the CPLD that start measures frequency mediumly to measure photograph tally, CPLD undertakes frequency measures the count of the photograph measuring, odd a machine inquiry to Right=1, show tally completes computation work, begin to read the data in taking CPLD. Otherwise, await. Odd the address that carries selector of the data in controlling CPLD selects an engine the Add[0 that tell end. .7] , read respectively take measure the frequency, 19 digit that measure photograph tally to occupy, have corresponding consideration. Program of frequency meter functor is called above all in computation, computation gives corresponding frequency, call program of phase meter functor again next, computation goes out corresponding phasic, call again into make transition program, will 16 become into the several transition that make 10 into make, call finally show child Cheng needs, tubal frequency, phasic value is shown in canal of 8 digit code. Because length concerns, here no longer expatiatory and particular program and the design of indication part. On one page 12 below one page

　　在电子测量科技中，测频测相是最根基的测量之一。相位测量仪是电子区域的常用仪器，当前测频测相主如果运用等精度测频、PLL锁相环测相的办法。研究发现，等精度测频法存在在整个测频规模内保持恒定的高精度的特点，可是该事理不克不迭用于测量相位。PLL锁相环测相能够实现等精度测相，但电路调试较简单。是以，选择间接测相法作为低频测相仪的测试办法[1、2、3、4]。

　　设计的低频测相仪，满足以下的科技指标：a .频率20-20KHz；b .输入阻抗≥100KΩ；c.相位测量相对误差≤1度； d.存在频率测量和数字显示性能；e.显示相位读数为0度--359度。

　　1系统工作事理