技术文摘：操纵Cadence最新方案，在芯片逻辑设计阶段解决时序、面积和功耗难题

Drop of dimension gradually as craft and the addition of chip complexity, how advanced paragraph of design, design a part to obtain accurate sequential information logically namely, get better balance in sequential, area and power respect thereby? How to forecast hypostatic layer correctly when logistic design (namely physical layer) material information? Become front logic to design the difficult problem that worker faces. In fact, when undertaking chip is designed (1) seeing a picture, area piece is given in what logistic circuit pursues medium inside, all circuit defer (Wire Delay) is same; But when undertaking real position and wiring, between component produced even the line very big change however. Be in these all connecting in the line, 80-90% belongs to this locality to connect a line (Local Wires) , that is to say yuan the circuit between parts of an apparatus is very short, won't bring what issue. But the length of additionally 10% winds a string, can produce serious sequential delay however normally, bring about sequential thereby cannot convergent. When encountering such real problem, front devises the typical way of personnel, be in namely integrated when raise stricter design requirement, have excessive restriction to the design (Over-constrain) , this numerical value is achieved normally 30% . But Over-constrain can bring about chip area to greaten directly, bar capacity increases, and be aimed at hereat, design personnel must have had power with respect to the addition of bar capacity again (Over-power) design, this numerical value is as high as 80%-90% even, great and wasteful resource. In addition, face design now for main low power especially, it is important that the action of sequential astringent amid is sent more. Narrow ceaselessly by 45nm of → of 65nm of → of 90nm of → of 0.18um → 0.13 Um as design technology, design personnel wants to consider 4 gist element when undertaking circuit is synthesized, they are respectively: The area is optimized, sequential is optimized, MVT(multi-threshold) and MSV(Multi-supply Voltage) . These raised taller requirement to EDA industry: Need offers the advanced solution that synthesis of contented much target, much mode is optimized and analysis, physics can forecast in time. Be aimed at hereat, cadence was recently on foundation of original science and technology, rolled out newest solution of updated Design With Physical. Graph 1: Logical View Vs. Solution of Design With Physical of method of Physical View Design With Physical basically includes two shares: Cadence already the Encounter RTL Complier that consign operates and First Encounter Silicon Virtual Prototyping(SVP) . According to Cadence Jack Chan of manager of market of science and technology of area of Asia-Pacific of design system company introduces, the place of the innovation of this Cadence, depend on First Encounter originally SVP function takes Encounter RTL Complier in integrated environment, make design personnel to be able to be in integrated environment thereby fast and interconnection of correctly understanding chip class. (2) seeing a picture pursues 2: Implementation of Design With Physical offers better interconnection mode to be in process of RTL-to-gate logistic framework, cadence is forecasted with PLE(physics layout) replaced a line to carry a model (Wireload Modes) . (Complier notes: The line carries a model is fan gives the ground (the number of Fanout) reckons with a few simple calculation wiring is laden, this kind of estimation is very coarse, because of its oversight fan goes out (the real position position with real Fanout Gates) , get good integrated result) very hard, PLE handles physical library and Floorplan information, consequently can the 90% this locality in rather guiding chip handle even the logistic framework of the line. And the SVP part of First Encounter, it is to use processing the rest technically 10% grow those who wind a string. Introduction Jack, of solution of Cadence newest Design With Physical roll out, simplified the design technological process of the member that chip front designs science and technology. In designing a process, science and technology member can be in environment of Encounter RTL Complier above all call PLE function, undertake circuit is synthesized; Later, assign the SVP function that transfers First Encounter through simple Predict_qos, with PLE together, undertake analyse and be optimizinged again to the design. (After 3) seeing a picture is done so can more essence of life grants the land beforehand whether does the circuit that appraise wants to back end stylist accord with meantime foreword to design a requirement. Graph 3: Appoint the SVP function convention that calls First Encounter to design flow Vs through simple Predict_qos. Design With Physical Jack is here special introduced to be in custom-built in changing a design, use the different result that traditional flow and place of solution of Design With Physical bring, see a picture 4: "In traditional flow, circuit synthesizes the time that spends 4 hours only, " Jack expresses, "But the result that place of these 4 hours produces is not the most accurate result, likely also sequential is very good, but should put hypostatic wiring layer do when optimizing, discovering a result is not the most satisfactory, drop is very big. We see appear in the graph, this is so called ' effect of arms to bang ' , science and technology member need just can get best result repeatedly. " on one page 12 below one page

跟着工艺尺寸的逐渐回升以及芯片简单性的增添，如安在前段设计，即逻辑设计部门获得正确的时序信息，从而在时序、面积以及功率方面获得更好的平衡？如安在逻辑设计时正确猜测实体层(即物理层)的具体信息？都成为前端逻辑设计工作者面临的难题。

事实上，在进行芯片设计时(见图1)，在逻辑电路图中的给定区块内，所有的线路延迟(wire delay)都是一样的；可是在进行理论结构和布线时，元件之间的连线却发生了很大转变。在所有这些连线中，80-90%属于本地连线(local wires)，也就是说元器件之间的线路很短，不会带来什么问题。可是此外10%的长绕线，凡是却会发生严重的时序延迟，从而导致时序无法收敛。

当碰到如许的实际问题时，前端设计人员的典型做法，就是在综应时提出更严酷的设计前提，对设计进行过度限度(over-constrain)，这个数值凡是达到30%。可是Over-constrain会间接导致芯周全积变大、栅容量增添，而针对于此，设计人员又不得不就栅容量的增添进行过功率(over-power)设计，这个数值甚至高达80%-90%，极大华侈了资本。

此外，面临当今尤为主要的低功率设计，时序收敛在其中的感化愈发主要。跟着设计工艺由0.18um→0.13 um→90nm→65nm→45nm不竭缩小，设计人员在进行电路分解时要思忖四概略素，它们分袂是：面积优化、时序优化、MVT(multi-threshold)以及MSV(Multi-supply voltage)。这些都向EDA行业提出了更高的要求：需要实时供给满足多方针分解、多模式优化和分析、物理可猜测的前进前辈解决方案。

针对于此，Cadence近日在原有科技根本上，推出了最新更新的design with physical解决方案。

图1：Logical View vs. Physical View

Design with Physical办法

design with physical解决方案首要包括两部门：Cadence已交付操作的Encounter RTL Complier和First Encounter silicon virtual prototyping(SVP)。据Cadence设计系统公司亚太区科技市场司理Jack Chan介绍，此次Cadence的立异之处，就在于将First Encounter本来的 SVP性能带入Encounter RTL Complier综合情况中，从而使设计人员能够在综合情况中迅速且正确地熟悉芯片级互联。(见图2)

图2：Design with Physical实现

为了在RTL-to-gate 逻辑架构过程中供给更好的互联模式，Cadence用PLE(物理结构猜测)包办了线载模子(wireload modes)。(编者注：线载模子是按照扇出(fanout)的数目和一些简单的计较来估量布线负载，这种估量很毛糙，因为它忽略了扇出门(fanout gates)真正的理论结构地位，很难获得精采的综分解果)，PLE操作物理库和floorplan信息，因而能够更正确地指点芯片中90% 本地连线的逻辑架构措置。而First Encounter的SVP部门，则是专门用来措置残余10%长绕线的。

Jack介绍，Cadence最新Design with physical解决方案的推出，简化了芯片前端设计科技员的设计流程。在设计过程中，科技员能够在Encounter RTL Complier情况中首先呼叫PLE性能，进行电路分解；之后，经由过程简单的predict_qos指定挪用First Encounter的SVP性能，与PLE一路，对设计进行分析和再优化。(见图3) 如许做之后能够更精准地预估到后端设计师所要的电路是否合适那时序设计要求。

图3：经由过程简单的predict_qos指定挪用First Encounter的SVP性能

传统设计流程 vs. Design with physical

Jack在这里特别介绍了在一个定制化设计中，采用传统流程和design with physical解决方案所带来的分歧成果，见图4：

“在传统流程中，电路分解只花4个小时的时候，”Jack暗示，“可是这4个小时所发生的成果并不是最切确的成果，也可能时序很好，可是当把实体布线层放上去做优化的时辰，发现成果并不是最满足的，落差很是大。咱们看到图中呈现的，这就是所谓的‘兵乓效应’，科技员需要几回才能获得最好的成果。”
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发布日期：2009-6-2　【返回】